The present invention is directed to branch protection circuitry provided to isolate a power network from a faulted load such as an overcurrent condition. The capability of isolating a power network from a faulted load is of significant importance, particularly in distributed power architectures. For certain applications, isolation of a power network from a faulted load is accomplished by fuses. Fuses are used in applications where low reliability is acceptable. In other applications, particularly where high power dissipation will occur, isolation of a power network from a faulted load is accomplished by placing a resistor in series with the power device.
It is the primary object of the present invention to provide a branch protection circuit having small dissipation and high reliability, which will latch off as long as a faulted load is present and will turn on after the fault has been removed. Conventional circuitry providing branch protection includes relatively complicated circuit means for measuring electric current flowing through a transistor. The branch protection circuit in accordance with the present invention is designed to sense only when electrical current flowing through a transistor exceeds a predetermined threshold value, but will not otherwise measure the specific value of the current flow. Accordingly, less expensive and less complicated circuitry is employed in the branch protection circuit in accordance with the present invention.
Typical prior art devices are exemplified by: Sears U.S. Pat. No. 4,202,023, issued on May 6, 1980 disclosing a circuit overload protector; Ganesan et al, U.S. Pat. No. 4,573,099 issued on Feb. 25, 1986 disclosing a CMOS circuit for providing overvoltage protection between a positive supply voltage rail and a negative supply voltage rail; Damiano et al U.S. Pat. No. 4,626,954 issued on Dec. 2, 1986 disclosing a solid state power controller with overload protection; Hechtman et al U.S. Pat. No. 4,795,920 issued on Jan. 3, 1989 disclosing a driver circuit for alternately sourcing current to, and sinking current from, a load and alternatively for presenting a high impedance thereto; Nadd U.S. Pat. No. 4,994,886, issued on Feb. 19, 1991 disclosing a composite MOS transistor and application thereof to a free-wheel diode structure; Wilcox U.S. Pat. No. 5,017,816, issued on May 21, 1991 for an adaptive gate discharge circuit for discharging the gate of a power FET transistor; Szetesi U.S. Pat. No. 5,018,041, issued on May 21, 1991 disclosing a current limiting circuit for instantaneously limiting the peak current of a fast high side power switch or power FET; Wodarczyk et al U.S. Pat. No. 5,023,692, issued on Jun. 11, 1991 disclosing a power MOS transistor having a current limiting circuit incorporated into the same substrate as the transistor; Hirota et al U.S. Pat. No. 5,027,251, issued on Jun. 25, 1991 disclosing a MOSFET device including a power MOSFET and a current mirror MOSFET which have drains coupled to each other; Elliott et al U.S. Pat. No. 5,029,269, issued on Jul. 2, 1991 to disclosing a delayed power supply overvoltage shut down apparatus for protecting a pulse-width modulated DC-DC power supply; Lee U.S. Pat. No. 5,088,018, issued on Feb. 11, 1992 disclosing an overvoltage protection power supply circuit for preventing an overvoltage from being applied directly to a flat panel display element; and Nakayama U.S. Pat. No. 5,105,251, issued on Apr. 14, 1992 disclosing a semiconductor device comprising first and second power MOS transistors which are formed on the same semiconductor chip in a common drain.
The branch protection circuit in accordance with the present invention disclosed herein provides simplified means for isolating a power network from a faulted load not taught or suggested by the aforementioned prior art. The circuit in accordance with the present invention is less complicated and economical than the conventional circuitry and devices disclosed by the above referenced prior art. Other advantages will become apparent from the following description.